home Electronic Before designing a switching power supply, must do analysis simulation and experiment

Before designing a switching power supply, must do analysis simulation and experiment

Loop control is an important part of switching power supply design. This article summarizes some of the currently available tools that allow you to calculate, simulate, and measure your prototype before starting to produce switching power supplies, so as to ensure safe and smooth production. This article will mainly discuss obtaining the dynamic response of the power stage and selecting the crossover frequency and phase margin.

Loop control is an important part of switching power supply design. This article summarizes some of the currently available tools that allow you to calculate, simulate, and measure your prototype before starting to produce switching power supplies, so as to ensure safe and smooth production. This article will mainly discuss obtaining the dynamic response of the power stage and selecting the crossover frequency and phase margin.

Get dynamic response of power level

As described in the article “Analysis, Simulation and Experiment One of the Design Prototype of Switching Power Supply”, the key to the compensation study of the specified switching converter is the power level Bode plot. There are several ways to obtain the Bode plot, the first of which is to use an average model in the SPICE simulation.

There are many versions of the average model, but the most commonly used is the 3-terminal PWM switch proposed by Dr. Vatché Vorpérian in 1986 and published in 1990. The original book introduced voltage mode control, but later versions also introduced current mode control, and only covered CCM. I deduced the automatic switching version of these models under VM and CM operating conditions in. A typical buck converter operating in current mode can be modeled as shown in Figure 7. The PWM switch is connected in a so-called common-mode passive configuration, where terminal p is grounded. The XPWM module is used to model the pulse width modulator, and the pulse width modulator is responsible for converting the error voltage set by the source V2 into a duty cycle. The gain of this natural sampling modulation module is the reciprocal of the sawtooth peak value Vp of the offset comparator: We assume that the sawtooth peak amplitude is 2 V, then the attenuation is 0.5, and the corresponding gain is -6 dB. After starting the simulation, you can Display the operating point and verify that it is correct. This is an important step to check whether the converter is working properly and the results provided are credible. Here, the model provides 5 V power to a 5 Ω load, which is what we expect. We can plot the result as the following figure: The peak amplitude response indicates that the quality factor Q is relatively high. This variable represents the circuit loss and depends on the overall efficiency. If you build a buck converter and plot its response, its attenuation may be greater than in Figure 8. This is because MOSFET RDS(on), various ohmic losses on capacitors and inductors, and freewheeling diode recovery losses will all cause circuit losses and affect Q.

If the load is now increased to 100Ω, the model will automatically be converted to DCM and provide a new graph obtained under the same 5V output condition when the duty cycle is set to 31%. The updated response is shown in Figure 9, and it can be confirmed that the peak gain disappears. Unlike other methods such as state space averaging (SSA), the buck converter operating under DCM is still a second-order system, but it is susceptible to low quality factor Q. This is very obvious when you see that the phase in the first-order model drops to zero under high-frequency conditions and continues to drop until it reaches -180°. Therefore, the response is composed of a low-frequency pole and a high-frequency pole, and the output capacitance and its equivalent series resistance (ESR) are zero in the transfer function. SPICE simulation provides a feasible solution that allows you to plot the control-to-output transfer function of the converter you want to stabilize. However, if the effects of parasitic elements (such as inductance and capacitance ESR) are truthfully modeled, it is impossible to know which items in the transfer function are affected by these spurious elements. Understanding the role of a given component in dynamic response is extremely important, because you should eliminate its adverse effects through appropriate compensation strategies. Except for Monte Carlo analysis or sensitivity analysis, which requires a lot of calculation time, the best method is to use a small signal model to determine the transfer function. Such a model is shown in Figure 10. This time we chose to use a buck converter operating under current mode control (CM). We can use the CM PWM switch that is very suitable for this type of analysis for this study. The model predicts sub-harmonic oscillations due to unstable current loop gain. By adding some slope compensation, the current loop gain can be effectively reduced and the converter can be stabilized. By calculating the number of energy storage elements with independent state variables, we can get the order of the converter: the third-order circuit, and we want to control the output transfer function, where Vc is the excitation voltage and Vout is the response voltage. There are many ways to determine the expression of the relationship between Vc and Vout, and I believe that no method can surpass the Fast Circuit Analysis Technology (FACT). Compared to the classic node/mesh analysis methods, they are not only the fastest methods, but they can also produce the so-called low-entropy effect. After the analysis is complete, the numerator and denominator will naturally appear in normalized form. The results obtained from this help us have an intuitive understanding of the transfer function: where are the poles and zeros, and which parameters have an effect on them. In addition, by understanding the parameters that affect the definition of zero or extreme points, you can effectively deal with natural differences in the production process. Dr. Raymond Ridley deduced the control-to-output transfer function of the CM buck converter (including the sub-harmonic pole at Fsw/2) in the paper he initiated. The details are as follows: in: In these expressions, the mc term is related to the external slope that is deliberately injected into the modulator to reduce the current loop gain. Mc is defined as follows: Se represents the external slope, with[V]/[s]as the unit, while Sn represents the inductance on-time slope adjusted by the inductive resistance Ri, also with[V]/[s]as the unit. For a buck converter, the inductance rising slope can be determined by the following formula: When mc=50%, the result shows that the audio sensitivity of the CM buck converter is theoretically zero.

Through, can draw the dynamic response graph of the power level, and decide where to choose the crossover frequency. Figure 11 shows that the peak response can be clearly seen when half of the switching frequency is reached. We have already seen how averaging simulations and the results obtained from the equations can achieve the power level response we need. The third option involves using a simulator that can deliver small signal responses through the switch circuit. This type of program is called a piecewise linear (PWL) simulator. SPICE is essentially a linear solver, any nonlinear characteristics must be linearized near the appropriate operating point. We can find this specific point by reducing the simulation step size until convergence is achieved. In the simulation process, non-linear components such as diodes must be replaced by a point-by-point linear approximation method. This process will not only overload the computer, but also cause convergence errors when the time step reduction algorithm reaches the lower limit. Simulators such as SIMPLIS® use the PWL engine to extract the AC response from the switching circuit. Figure 12 shows a typical modeling method for a diode. You can see how these linear parts describe the relationship between the increase in forward voltage drop and the diode current. They can effectively replace the Shockley exponent equation describing the diode current. No matter where the operating point of the diode is, its characteristic is linear, only the slope changes. This eliminates the need for additional linearization algorithms, because the circuit is always a linear circuit. Therefore, AC modulation can be used as the excitation of the switching circuit to obtain a small signal response. A typical LLC converter is shown in Figure 13. In the new current-mode control method proposed by NCP13992, the high-side and low-side MOSFETs operate with an accurate duty cycle of 50%. The high-side transistor turns on and maintains this state until the Inductor peak current reaches the target value required by the feedback loop. When the high-side transistor is turned off, the low-side transistor is activated during the turn-off period of the previous ton time to ensure an accurate 50% duty cycle. The proposed circuit is a simplified version of the complex control circuit part, but it allows the use of SIMPLIS demo version Elements to simulate the entire circuit. After tens of seconds, the simulator will not only provide the waveform of each cycle (you can check the rms, average or peak value, etc.), but also provide a control-to-output transfer function. These two results are shown in Figure 14 and Figure 15:  This is interesting because you don’t need to use an averaging model, and you can explore second or third order effects (such as changes in RDS(on)) and immediately see its impact on the transfer function. There are equation-based models for LLC converters, but due to their complexity and the large amount of mathematical calculations involved, I think this type of model is more difficult to use. It is indeed an interesting method to obtain analog data mixed with transient and small signal results in a short period of time.

Select crossover frequency and phase margin

Now that we have the power stage transfer function, the next step is to select and apply a compensation strategy. This step is crucial. The first question is, how to choose the crossover frequency fc and phase margin? A large number of suggestions are provided in the literature, ranging from 1/5 to 1/10 of the switching frequency Fsw. If the upper limit of the converter’s crossover is obviously Fsw/2, then the adopted topology will also put forward other restrictions. Let’s get started:

Topological structure derived from step-down: LC network will impose a resonant frequency f0. If you observe the power stage control to the output transfer function under voltage mode control, you will find that the gain peaks at f0. Therefore, at this frequency, the loop must have some gain so that the oscillation can be corrected. Therefore, it is best to choose at least 3 to 5 times the resonant frequency fc. In current mode control, the situation is relatively simple, because the response of the low frequency part is a first-order response. However, due to the existence of non-attenuated sub-harmonic poles, the gain may reach a peak at Fsw/2. Then, slope compensation is needed to suppress these poles and stabilize the converter gain. Topological structure derived from buck/boost: In these structures, energy is transmitted in two steps. First, the energy is stored in the inductor during the turn-on period, and then it is released to the load during the turn-off period. In the case of sudden demand for output power, the converter cannot respond immediately because the inductor needs more cycles to increase energy storage. This inherent response delay is embodied as the right half-plane zero (RHPZ) in the control-to-output transfer function. RHPZ can increase the amplitude (like other zeros), but it will cause a phase lag. It is opposite to the zero point of the left half plane with the phase leading. When there is RHPZ in the transfer function, the power stage phase will decrease further as you approach the zero position. Therefore, it is recommended to cross over before RHPZ appears. A better approach is to select the upper limit of fc to 20-30% of the lowest position of RHPZ (obtained by the maximum current and the minimum input voltage). This applies to the VM and CM control methods because the RHPZ position is the same in these two methods. In the VM, you must follow the buck rule, that is, the selected fc is 3-5 times greater than f0, but this time the movement of f0 is related to the duty cycle, which makes the final choice more complicated.

Boost topology: its characteristics are almost the same as the topology derived from the above-mentioned buck/boost. RHPZ and resonance exist in voltage mode control. The flexibility of current mode control is slightly greater than that of VM, because you don’t need to reach the peak at f0, but in any case, RHPZ will limit the upper limit of fc. If you want to use a boost or buck/boost converter to achieve bandwidth, it is best to reduce the inductance value so that the converter can respond more quickly to sudden output power demands. All of the above recommendations are summarized in Figure 16. Please note that pushing the crossover frequency too high when the topology allows it is not a wise decision. This is because using a wide bandwidth is like opening a funnel: the converter does become faster, but it also becomes more sensitive to external disturbances and noise: adjust fc to meet specific transient specifications and don’t let it exceed this value.

The choice of open-loop phase margin depends on the type of transient response required. If you want to respond quickly and accept a little overshoot, a phase margin of about 50° is sufficient. If you want to be more conservative and accept a slower response (or recovery) without overshoot, then 70-80° would be a better phase margin. You can find the correlation between the open-loop phase margin jm and the closed-loop quality factor Qc through the graph shown in Figure 17. This is a theoretical method that describes how a second-order system with origin poles and high-frequency poles (no zeros) behaves under closed-loop conditions.

One thing we must be clear is that the choice of phase margin depends not only on the application, but also on the acceptable limits. For example, if the converter will experience a large temperature change (for example, the ambient temperature range is -40 to 80°C), it is best to choose a high margin (80-90° or higher) and observe that it will How low is it down. Too low phase margin and response may cause unacceptable trip protection. In my opinion, 40° is an appropriate absolute minimum. If the power supply is operated at room temperature where the ambient temperature never exceeds 35°C and below 0°C (most consumer products), the less aggressive goal may be easier to achieve. After the design is determined, you must perform a lot of experiments (for example: Monte Carlo analysis or worst-case analysis) and ensure that the phase margin will never drop below 40° in the dilemma simulation. As emphasized in the literature, a large phase margin will not only extend the recovery time, but also reduce the low-frequency gain, which prevents the converter from suppressing low-frequency disturbances (120 Hz ripple of AC/DC switching). The figure below shows the typical transient response of two different phase margins at a constant crossover frequency (Figure 18). The gain margin depends on the open loop gain changes that your system experiences during operation. According to the change of the error amplifier open-loop gain (manufacturing process, temperature, etc.), if there is input feedforward or no input feedforward, etc., the loop gain amplitude will move up and down, thereby affecting the crossover frequency. Generally, a gain margin of 15-20 dB is considered a conservative value to ensure a robust design.