TI’s DS90UB913Q/DS90UB914Q chipsets are 10MHz~100MHz 10-bit/12-bit FPD-Link III SER/DES, providing high-speed FPD-Link III interface and high-speed forward path and bidirectional control path for data transmission on differential pairs. Mainly used in the connection between the image and the video processor of the car ECU, and mainly used in the car video system, the front-end camera of the anti-collision system, the rear-view mirror camera and the auxiliary management of the parking system.
The DS90UB913Q/914Q chipset has an FPD link III interface, a high-speed forward channel, and a single differential pair, a two-way control channel for data transmission. The DS90UB913Q/914Q chipset includes a high-speed forward channel and a two-way control data channel differential signal. The serializer/deserializer is used for the connection between ECUs (Electronic Control Units), imaging and video processors. This chipset is very suitable for driving 12-bit internal pixel depth/two-way control channel bus, two synchronous signal video data.
There is a multiplexer on the deserializer to select between the two input imagers. The deserializer can have only one valid input imager. Primary video transmission converts 10-bit/12-bit data on a single high-speed serial data stream, and simultaneously performs separate, low-latency, two-way control channel transmission, and receives control information from the I2C port, which is blanked in the video The period is independent.
Use TI’s embedded clock technology to perform information-transparent full-duplex communication on a single differential pair, and transmit asymmetric bidirectional control channel information in both directions. By eliminating the problem of deviation between parallel data and clock paths, this single serial data stream simplifies the extensive transmission data bus on the PCB, which greatly saves system costs, reduces the data path, and reduces the number of PCB layers. The width of the cable, and the size and pin of the connector. In addition, the input of the deserializer provides adaptive equalization to compensate for losses over long distances. It uses internal DC balanced encoding/decoding to support AC coupled interconnection. The serializer uses a 32-pin LLP package, and the deserializer uses a 48-pin LLP package.
Figure 1 Typical application block diagram of DS90UB913Q/DS90UB914Q
Figure 2 Outline drawing of DS90UB913Q/914Q evaluation board
Main features of DS90UB913Q/914Q
• 10 MHz~100 MHz input pixel clock support
•Single difference pair interconnection
• Programmable data payload
-10-bit payload up to 100MHz
-12-bit payload up to 75MHz
• Continuous low-latency two-way control interface channel @400kHz I2C support
• 2:1 multiplexer, select two input imagers
• Embedded clock has DC balance coding to support AC-AC coupling interconnection
• The longest can drive 25m shielded twisted pair
• 4 dedicated general-purpose inputs (GPI)/outputs (GPO)
• LOCK output report pin and high-speed BIST diagnostic function to verify the integrity of the link
•Integrated terminal resistance
• 1.8V, 2.8V or 3.3V compatible parallel input serializer
• 1.8V single power supply
• Comply with ISO10605 and IEC61000-4-2 ESD
• Operating temperature range -40℃~+105℃.
•Small serializer (5mm×5mm)
• The deserializer does not require a reference clock
• Adaptive receive equalization
• EMI/ EMC reduction
-DES Programmable Spread Spectrum (SSCG) output
-DES receive interleaved output
•Automotive Vision System
• Front camera, collision mitigation
• Rear view camera, backup protection
DS90UB913Q/914Q Evaluation Board
The DS90UB913Q/914Q evaluation circuit board consists of two parts. The first part of the circuit board provides a point-to-point interface for sending, parallel video data. The second part can carry out I2C bus control, MCU/FPGA, two-way control communication, and remote peripherals can be programmed through the serializer.
Through a two-wire serial data stream, the DS90UB913Q/914Q chipset supports a variety of automotive megapixel camera systems. The single differential pair (FPD-Link III) is suitable for the connection between the imager and the host controller/electronic control unit (ECU)/FPGA. The bidirectional control channel of DS90UB913Q/914Q provides seamless communication between ECU/FPGA and imager module. Through the same serial video link, a transparent bidirectional control channel (I2C) is used to transmit full-duplex high-speed video data (10/12-bit parallel data, two SYNC bits and PCLK). In addition, there are 4 unidirectional general (GPI and GPO) signal lines from the deserializer to the serializer. The interface can be transparent (not dependent on the video blanking interval), full-duplex communication on a single high-speed differential pair. The serializer and deserializer carry out data communication at the PCLK clock speed, ranging from 10MHz to 100MHz, and the highest I2C bus rate is 400kbps (25m cable length, -40~+105℃).
Main features of DS90UB913Q/914Q evaluation board
•Rosenberger connector on board, and Leoni-Dacar cable (not included)
• Optional single-ended coaxial connector is shared with coaxial cable
•Support a variety of car megapixel cameras through two-wire serial data stream,
• Only need a 5V power supply
• Power transmission through coaxial cable, or differential pair power transmission
• Realize high-speed video data transmission through a twisted pair cable, integrated low-latency two-way control
• Through a bidirectional I2C bus control channel, output 10-bit/12-bit parallel data, two SYNC bits and PCLK
• Four additional one-way general purpose (GPI, GPO) signal lines from serializer to deserializer
• Through a high-speed differential pair for full-duplex communication and asymmetric two-way control, there is no video signal blanking interval
• Send data at PCLK clock speed, ranging from 10MHz to 100MHz
• I2C bus rate up to 400kbps